In a variety of applications it is desirable to apply particles to a substrate in a predetermined pattern. One such application is the formation of patterns of solder alloy on silicon wafers. The precision required to appropriately form the desired pattern renders traditional powder application methods insufficient. A typical silicon wafer substrate may have a relatively high concentration of connection points present as exposed metallization such as pads or under bump metallization (UBM) at a diameter of, for example, about 100 microns and spaced at a pitch of about 250 microns.
U.S. Pat. No. 5,817,374 discloses a process for patterning powders which employs a bed of particles, a mask, and a dielectric receptor. The dielectric receptor receives a temporary charge, which attracts the particles so they travel through the mask and adhere to the receptor in a pattern defined by the mask.
In addition, it is important to ensure that the particles are deposited in the desired pattern without irregular or stray particle distribution. Many deposition processes result in a so-called “edge effect,” where there is a non-uniform band of overdeposited metal particles around the periphery of the metallization. Reducing the edge effect during deposition is desirable to provide uniformity in the final product.
Mixed-electronic component substrates allow a variety of functions to be accomplished by a single substrate, but they require varying solder bump thicknesses appropriate for the discrete components. Creating a substrate with varying thicknesses is a cumbersome process using traditional stencil printing methods because it requires a special stencil which must be cleaned after each deposition. As such, it would be desirable to develop a single-step method of creating substrates with controlled solder bump thicknesses thereon.